The present invention relates generally to the field of semiconductor manufacturing and of integrated circuit fabrication. More particularly, the present invention relates to complementary metal oxide semiconductor (CMOS) field effect transistors (FET) with strained silicon for high performance and a method for manufacturing the same.
Since it has become increasingly difficult to improve metal-oxide-semiconductor-field-effect transistor (MOSFET) performance through continued scaling, methods enhancing performance of MOSFETs without scaling have become important. Strained silicon (Si) has shown enhancement of mobility for both electrons and holes. Therefore, in contemporary CMOS technology, there is significant interest and work in the use of strained material for the FET channel.
In one approach, silicon-germanium alloy (SiGe) is used to form a surface channel strained Si/relaxed SiGe n-type MOSFET (NMOSFET or NFET). In that approach, biaxial tensile strain is induced in a very thin epitaxial Si layer. The tensile strain reduces the effective mass of the electrons, which results in enhancement of electron mobility.
In the case of a p-type MOSFET (PMOSFET or PFET), the germanium (Ge) concentration must be greater than about 30% in order to have an effective increase in hole mobility.
This approach has the following drawbacks: 1) The strained silicon is grown on relaxed SiGe, and therefore it is difficult to control the leakage of devices.
2. The requirement for enhanced performance of more than 30% germanium concentration further increases the defect density.
3. The high diffusivity of dopant, such as arsenic and phosphorus, in SiGe makes it difficult to form shallow p-n junctions. For sub-micron or deep-sub-micron MOSFETs, shallow junctions are required to scale devices.
Thus, the art has a need for a method of making circuits having the benefits of strained silicon without the low yield characteristic of the prior art.